The buried resistor, also called a diffusion resistor, has been used in MOS circuits. In CMOS technology, a buried resistor consists, for example, of a N-type doped region in a P-well, with an intrinsic (or doped) polysilicon layer overlying the N-doped region which is isolated from the polysilicon by an oxide layer. The length of the resistor is defined by the polysilicon which is formed at the same time as the MOS device polysilicon gate. Known in the art are two types of buried resistors: (1) one with a block mask covering the entire resistor region and (2) one without such a mask. The block mask prevents the source and drain doping from entering the resistor region. Without the block mask, the N-type source and drain doping will be applied to the resistor terminal region resulting in heavily doped polysilicon.
The manufacturing of the buried resistor is compatible with MOS technology. The polysilicon and the isolation oxide layer are done along with the MOS device formation. The sheet resistance can be accurately and tightly controlled.
The buried resistor with the block mask has certain characteristics only some of which are desirable. First, this type of buried resistor has low gate capacitance and good reliability. These are desirable characteristics. Among the undesirable characteristics are the following. First, the input and output terminals of the buried resistor with the block mask tend to form an undesirable non-ohmic contact when the block mask is used. This disadvantage becomes significant as the buried resistor gets shorter. Second, the end resistance or spreading resistance is high without the source and drain doping. The large spreading resistance makes the layout inefficient since one has to make the resistor width wide to keep the length/width ratio small. A third disadvantage is that the parasitic buried resistor junction capacitance is high. Finally, there is significant chip-to-chip variation of the short resistor.
The buried resistor without a block mask has lower spreading resistance, good ohmic contact, and less variation from chip to chip. Since the polysilicon is highly doped, it has the following undesirable characteristics: (1) poor reliability due to the high field across the oxide, and (2) the parasitic capacitance of the buried resistor to polysilicon layer is high.
Furthermore, both types of resistor designs, i.e., with and without a block mask, have high parasitic junction capacitance.
FIG. 1 shows a prior art buried resistor cross-section 10 without the block mask. FIG. 2 shows a prior art buried resistor layout 30 with a layer of block mask 32. More particularly, FIG. 1 shows buried resistor cross section 10. Buried resistor 12 is N+ doped. Input 14 and output 16 are at the top of buried resistor 12. In between input 14 and output 16 lies N+ S/D doped polysilicon gate 18. A P-well 20 lies under buried resistor 12. N+ source/drain doping have been added under the input 14 and output 16 terminals and in the intrinsic polysilicon gate 18. The area marked 24 is the shallow trench isolation for the buried resistor 10. FIG. 1 has no block mask.
FIG. 2 shows a prior art buried resistor layout 30 with the block mask 32. The block mask 32 covers the entire buried resistor 34. Input terminal 36 is on the left of intrinsic polysilicon gate 38. Output terminal 40 is to the right of intrinsic polysilicon gate 38.